1. Field of the Invention
The present invention generally relates to digital integrated circuits and, more particularly, to sequential logic circuits and systems such as digital clock generators and latch arrays used in the datapaths and control paths of microprocessors, and other electronic digital systems. More specifically the invention relates to a pulse-to-static conversion with a self-timed control circuit latch for systems designed with dynamic circuits, and to the interfacing of dynamic and static circuits.
2. Description of the Prior Art
It is usual to classify digital switching networks into two categories: combinatorial and sequential. Combinatorial switching networks are those whose outputs only depend on the present inputs. Sequential switching networks are those whose outputs depend on the past sequence of inputs as well as on the present inputs. Such circuits store information about the previous history of the inputs in storage elements called latches and/or registers. The information stored in latches and registers can be updated (a new state replacing a present state) in a controlled and predictable manner by triggering from a periodic global clock signal distributed throughout the digital system. The global clock ensures that all memory elements change state at approximately the same time. Systems which are synchronized to a global clock are called synchronous. Conversely, asynchronous systems have no global clock distribution, but instead require self-timed circuit techniques.
Synchronous systems require synchronization of the setting of latches to the global clock. Referring to FIG. 1, a conventional prior-art level sensitive D-latch is shown. The output of the latch follows its data-input for all the time that the clock maintains a given level. In CMOS this latch is constructed from two transmission gates and two CMOS inverters. The inputs are a data input, D1, and a clock and its complement, CLK and CLKN, respectively. The outputs are Q1 and its complement Q1N.
Referring to FIG. 1, when the clock is high, "H", Q1 obtains the value of D1 and the feedback path from the output of inverter I1 to the input of inverter I2 is broken (open). Conversely, when CLK="L" the feedback path is established and the input D1 is disconnected. Hence the output depends upon the level of the clock signal; as long as CLK="H", Q1 samples D1 continuously. The latch in FIG. 1 is positive level sensitive. By reversing the control signal connections to the transmission gates, a negative level sensitive latch can be formed.
Master-slave and edge-triggered registers are known to have improved reliability. A positive-edge-triggered D register, formed by combining a negative level-sensitive latch with a positive level-sensitive latch is shown in FIG. 2. The first stage latch is the "master", the second the "slave". In edge-triggered registers the data input is sampled only during a transition (edge) of the clock. As shown in the waveforms, in the example of FIG. 2, the output Q takes on the value of the input D only at the times of the positive (low-to-high) transitions of the clock, CLK.
Combinatorial logic can be formed from a wide diversity of circuit techniques. These techniques can be broadly divided into two categories: static and dynamic. Most often, if the performance constraints allow, static logic is used wherever possible, for expediency, simplicity and reliability. Static CMOS circuit nodes undergo at most a single transition during the course of a logic cycle (system clock period). However, with increasing pressure for ever higher performance, digital designs are increasingly employing dynamic circuit techniques in critical paths, both in datapaths and control paths. Dynamic circuits are characterized by circuit nodes which are typically discharged as quickly as possible at the time of logic evaluation, and then later in the cycle these nodes are pre-charged, i.e. reset, back to their initial, standby values. That is, if in a logic cycle a dynamic node is discharged, then later in that same cycle the node is re-charged back to its initial state. There are two transitions within the cycle, in contrast to one transition for a static node. Thus the waveforms on dynamic nodes are pulses of duration less than the cycle time.
FIG. 3 shows a comparison of the waveforms on the dynamic and static circuit nodes for similar bit-patterns. For example, DYN1 shows a dynamic node and ST1 a static node for a 1-1-1-0 bit pattern. For the dynamic node a "1" is represented by the presence of a unipolar pulse, whereas a "0" is represented by the absence of a pulse, during a clock period. In contrast, for the static node a "1" is represented by a high voltage level and a "0" by a low voltage level. Notice that a complete pulse is generated during each cycle for an active ("1") dynamic node, whereas for a static node at most a single transition occurs during a cycle, and in cases of consecutive same-bits the static level does not change. The bottom two waveforms show a dynamic node, DYN2, and a static node, ST2, for a different bit pattern, 1-0-1-0.
The implication for registers in a synchronous design are that if the inputs to the registers are dynamic then the registers must "capture" pulses, whereas if the inputs are static the register need only detect a level, at for example, the time of one of the clock edges. For the arbitrary dynamic pulses shown in FIG. 3, neither the level-sensitive D-latch of FIG. 1, nor the edge-triggered register of FIG. 2 would detect the dynamic "1" state. The fact is that prior-art latches and registers similar to FIGS. 1 and 2 are in general inadequate for capturing and storing the information content from dynamic inputs.
For the purpose of reviewing the merits of dynamic and static circuits, an example comparison of 3-input AND gates is shown in FIG. 4, for three different styles of logic. FIG. 4(a) shows the conventional static CMOS circuit. Two styles of dynamic circuits are shown in FIGS. 4(b) and 4(c). FIG. 4(b) is the corresponding domino-logic circuit and FIG. 4(c) is the corresponding self-resetting case.
The domino-logic circuit operation is tightly synchronized to the system clock. When the clock is low, the pre-charge device is held on and this pre-charges the dynamic node high. This is the standby mode. When the clock is active high, the pre-charge device is off and the tree of NMOS devices is enabled. The domino inputs must be valid during the clock-active period. In this example, if all inputs, IN1, IN2 and IN3 are active when the clock is high, the dynamic node will be discharged and the output will rise to "H". Then when the clock goes low again the pre-charge device turns on and resets the dynamic node to its standby-high state, and subsequently the output resets to "L".
The self-resetting case differs most significantly from the domino-case in that resetting of the dynamic node is totally independent of any system clock. Rather, the reset is derived locally either by feedback from downstream logic, or from a local timing chain triggered by an input upstream. That is, the circuit is self-resetting, or self-timed. During standby the RESET signal is high, "H". Therefore, to prevent the dynamic node (labelled "quasi-dynamic node" in FIG. 4(c)) from gradually discharging due to leakage during this standby period a small standby device, QS, is held on by feedback from the output (the output inverter and QS from a "half-latch").
In FIG. 4 the numbers next to the devices are relative device widths. The sum of all device widths gives an approximate size comparison among the three circuits. Summing the widths it can be seen that the static circuit is about 50% larger than either dynamic circuit. The generalization is true that dynamic circuits occupy less area, primarily due to the fact that there are fewer PMOS devices. Furthermore, the dynamic circuits are generally faster than static circuits, because there are fewer PMOS devices loading the dynamic outputs. The outputs of FIG. 4 go to inputs similar to the inputs of the FIG. 4 circuits. Less gate capacitance loading, again due to fewer PMOS load devices, also leads to lower power dissipation for the dynamic circuits. In short, dynamic circuits are faster and smaller than static circuits, and for a given cycle time dissipate less power.
However, static circuits have a significant advantage in ease of design. Static circuits avoid the pre-charging and clock distribution that are necessary for domino-logic, and avoid the resetting necessary in the self-resetting CMOS case. Furthermore, the noise margins for static circuits are larger than for dynamic.
Comparing the dynamic circuit cases, SRCMOS has the potential advantages over domino-logic of higher performance because of the absence of any clocking devices in the logic trees, and greatly reduces the loading on any system clock, thereby alleviating clock skew and power problems. However, SRCMOS is more difficult to design at the system level because of the lack of the global synchronization provided by a global clock.
Hence, it is seen that there are various pros and cons among the variety of static and dynamic circuit techniques. Consequently for high-performance designs it is advantageous to choose a mix of static and dynamic circuits, utilizing dynamic circuits where performance, area and power are a premium, and using static elsewhere. Thus, in order to reap the benefits of mixing logic circuit types in combinatorial logic, there is a need for fast pulse-to-static converters and pulse-to-static conversion latches in order to interface dynamic circuits with static circuits.
A further need for pulse-to-static conversion latches occurs in the case of driving long lines wherein load capacitances are dominated by line-capacitance, rather than gate capacitance. Such cases occur for example when one logic sub-system has to interface to another sub-system some non-negligible distance across the chip. In these cases less power will be dissipated if the long lines carry static signals rather than dynamic. The reason for this is as follows: Power dissipation in the long line occurs only when the line is charged up to the high voltage level, "H". Referring back to FIG. 3, it is evident that such charging takes place in dynamic lines whenever there is a 0-to-1 or 1-to-1 transition. In these situations a complete pulse is created, which first charges, and then discharges the line capacitance. However, in the case of static signals, charging of the line capacitance only occurs for a 0-to-1 transition, which can only occur at most once every two cycles. Thus for worst-case patterns, 1-1-1-1 . . . for dynamic, and 0-10-1 . . . for static, the static case will dissipate only half as much power as the dynamic case. That is, the "switching factor" for static circuits is at most one-half the dynamic-value, and in most practical cases the ratio is even smaller.
A concern in modern VLSI circuits, which can contain millions of transistors, is designing-for-test. This concept considers how a design can be effectively tested, right from the inception of the design, and specifically how to include appropriate test facilities.
One common technique is to make the register comply with the Level Sensitive Scan Design (LSSD) methodology. In the LSSD methodology, registers are constructed in a way such that they can be converted to shift-registers which can be serially interconnected. In the LSSD test mode test data can be shifted into the registers before performing a normal logic cycle, and then the results can be subsequently shifted out and compared with expected results.
An alternative test methodology specifically for self-resetting CMOS circuits is the "static-evaluate" mode. In the static-evaluate-mode, the dynamic circuits are converted to ratioed, pseudo-nmos circuits which reset automatically, at a slow rate, when the circuit inputs are reset. This enables slow-speed testing of functionality.